AN IMPROVED PERFORMANCE OF MINIMUM COST SPANNING APPLICATION FOR VLSI INTERCONNECTS Mohamed Faidz Mohamed Said #1 # Universiti Teknologi MARA 70300 Seremban, Negeri Sembilan, MALAYSIA 1 faidzms@ieee.org Abstract—Elmore delay is extensively used model in both digital circuit interconnects design and analog that recent to compute signal delays. General Elmore delay models was used in the studies of various process in delay technologies [1]. Besides the Elmore delay model, different delay model presented in the literature that contain inductive effects in order to increase accuracy (an analytic delay). The person that was applied this model to RC circuit is Rubinstein et al in 1983[2]. The classical Elmore delay general form is defined then solve by applying the indicated boundary. The input signal effect of the rise is considered in [3]. The classical Elmore and the new improvement of Elmore delay was compared by using SPICE simulation that the result varies the accuracy of delay formation. The result shows that an improved delay interconnection provided a better precision. Keywords: VLSI Interconnects, Elmore Delay REFERENCES [1] A. Goel and Y. Huang, "Modelling of parasitic interconnection inductances on the GaAs-based VLSIC's," Mathematical and Computer Modelling, vol. 14, pp. 349-353, 1990. [2] J. Rubinstein, P. Penfield Jr, and M. A. Horowitz, "Signal delay in RC tree networks," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 2, pp. 202-211, 1983. [3] S. Kim and S. S. Wong, "Closed-form RC and RLC delay models considering input rise time," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 54, pp. 2001-2010, 2007. [4] H. B. Bakoglu, "Circuits, Interconnections, and Packaging for VLSI," 1990. [5] F. Tsui and D. Gao, "ANALYSIS OF TREES OF TRANSMISSION LINES." [6] S. I. Association, National technology roadmap for semiconductors: SIA, 1997. [7] J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," Integration, the VLSI journal, vol. 21, pp. 1-94, 1996. [8] Y. Eo and W. R. Eisenstadt, "High-speed VLSI interconnect modeling based on S-parameter measurements," Components, Hybrids, and Manufacturing Technology, IEEE Transactions on, vol. 16, pp. 555-562, 1993. [9] J. Cong, K.-S. Leung, and D. Zhou, "Performance-driven interconnect design based on distributed RC delay model," in Design Automation, 1993. 30th Conference on, 1993, pp. 606-611. [10] J. B. Kruskal, "On the shortest spanning subtree of a graph and the traveling salesman problem," Proceedings of the American Mathematical society, vol. 7, pp. 48-50, 1956. [11] R. C. Prim, "Shortest connection networks and some generalizations," Bell system technical journal, vol. 36, pp. 1389-1401, 1957. [12] M. Avci and S. Yamacli, "An improved Elmore delay model for VLSI interconnects," Mathematical and Computer Modelling, vol. 51, pp. 908-914, 2010. [13] A. I. Abou-Seido, B. Nowak, and C. Chu, "Fitted Elmore delay: a simple and accurate interconnect delay model," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 691-696, 2004. [14] R. Gupta, B. Tutuianu, and L. T. Pileggi, "The Elmore delay as a bound for RC trees with generalized input signals," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 95-104, 1997.