APPLICATION OF PARALLEL PROCESSING - A CASE STUDY ON FPGA BASED ON RECONFIGURABLE COMPUTER

Nur Izni Syahirah binti Hassim #1, Mohamed Faidz Mohamed Said #2

# Faculty of Computer & Mathematical Sciences, Universiti Teknologi MARA
70300 Seremban, Negeri Sembilan, MALAYSIA

1   nurznihassim@gmail.com
2   faidzms@ieee.org

 
Abstract—Reconfigurable computing is an assuring technology that accommodates the present and future computational demands. An example of the extreme notch of parallelism created in reconfigurable hardware materials is the field programmable gate arrays (FPGAs). Though, despite their capable performance, reconfigurable computers are still to be widely applied. It is because reconfigurable computer has the lack of mutual and intuitive operating system. The goal of this research is to explore the feasibility of providing a systematic processing and to understand the view into reconfigurable computer through Operating System without incurring significant performance penalties. Comportment of hardware is the key characteristic of Reconfigurable Computing is that it can be reconfigured to be applied in a particular functionality that is more suitable for specifically fitted in hardware than on a simple uniprocessor. Reconfigurable computing systems connect with the programmable hardware and microprocessors, in order to have the improvement of the combined strengths of software and hardware that will be used in applications alternating from embedded systems to high performance computing.

Keywords: Field Programmable Gate Arrays, FPGA, configurable computer



REFERENCES

[1]	Hofmann, A., et al. Reconfigurable on-board processing for flexible satellite communication systems using FPGAs. in Internet of Space (TWIOS), Topical Workshop on. 2017. IEEE.

[2]	Kuwahara, T., et al., FPGA-based operational concept and payload data processing for the Flying Laptop satellite. Acta Astronautica, 2009. 65(11–12): p. 1616-1627.

[3]	Mostert, S. and E. Kriegler, Implementing an image processing system for the next generation Earth observation sensors for the SUNSAT 2 micro-satellite programme. Acta Astronautica, 2005. 56(1): p. 171-174.

[4]	Schmidt, A.G. and T. Flatley, Radiation Hardening by Software Techniques on FPGAs: Flight Experiment Evaluation and Results. 2017.

[5]	Majer, M., et al., The Erlangen Slot Machine: A dynamically reconfigurable FPGA-based computer. The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2007. 47(1): p. 15-31.

[6]	Liu, H., Y. Zhao, and G. Xie. Image segmentation implementation based on FPGA and SVM. in 2017 3rd International Conference on Control, Automation and Robotics (ICCAR). 2017.

[7]	Ahilan, A. and P. Deepa, Design for built-in FPGA reliability via fine-grained 2-D error correction codes. Microelectronics Reliability, 2015. 55(9–10): p. 2108-2112.

[8]	Baklouti, M., et al., FPGA-based many-core System-on-Chip design. Microprocessors and Microsystems, 2015. 39(4): p. 302-312.

[9]	Laxmi, V., C.S. Adiga, and S. Harish. FPGA based Reconfigurable Computing Systems: A New Design Approach-A Review. in Advanced Materials Research. 2012. Trans Tech Publ.

[10]	Kindratenko, V. and D. Pointer. A case study in porting a production scientific supercomputing application to a reconfigurable computer. in 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. 2006.

[11]	Nivin, R., J.S. Rani, and P. Vidhya. Design and hardware implementation of reconfigurable nano satellite communication system using FPGA based SDR for FM/FSK demodulation and BPSK modulation. in 2016 International Conference on Communication Systems and Networks (ComNet). 2016.

[12]	Sharma, S., et al. FPGA Implementation of M-PSK Modulators for Satellite Communication. in 2010 International Conference on Advances in Recent Technologies in Communication and Computing. 2010.

[13]	Irwansyah, A., et al., FPGA-based multi-robot tracking. Journal of Parallel and Distributed Computing, 2017. 107: p. 146-161.

[14]	Mandal, S., et al., Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware. Microprocessors and Microsystems, 2017. 51: p. 313-330.

[15]	https://www.youtube.com/watch?v=D3vD4d5LfbQ&rel=0

[16]	M. F. M. Said, M. N. Taib, and S. Yahya, "Analysis of the CPU Utilization for Point-to-Point Communication Operations in a Beowulf Cluster System," in 2008 International Symposium on Information Technology, 2008, pp. 1-6.

[17]	M. F. M. Said, M. N. Taib, and S. Yahya, "Analysis of TCP/IP Overhead on Overlapping Message Transfer and Computation in a Distributed Memory System Architecture," International Journal of Advanced Research in Computer Science (IJARCS), vol. 3, pp. 22-36, 2012.

[18]	M. F. M. Said, S. Yahya, and M. N. Taib, "Analysis of Different Programming Primitives used in a Beowulf Cluster," International Journal of Computer and Information Technology (IJCIT), vol. 1, pp. 25-33, 2012.