BIT-LEVEL PARALLELISM - A CASE STUDY ON A 32-BIT MICROPROCESSOR

Mohammed Said bin Mohd Isa #1, Mohamed Faidz Mohamed Said #2

# Faculty of Computer and Mathematical Sciences, Universiti Teknologi MARA
70300 Seremban, Negeri Sembilan, MALAYSIA

1 mohammedsaidofficial@gmail.com
2 faidzms@ieee.org

 
Abstract—The finest grain parallelism is a definitive method for getting the most extreme execution. Bit-level parallelism is the finest grain that can ever be accomplished. Bit-level parallelism is additionally simple to misuse and see hypothetically in light of the fact that it is only a truth table. Issues related with bit-level parallelism, for example, equipment confinement and confirmation methods are being overcome by advances in expansive scale coordination (VLSI) and compiler innovations. With the appearance of XILINK pin grid array (PGA), abusing bit-level parallelism is no longer a fantasy yet there are a few issues which must be considered. The advancement of chip design relies on the changing parts of innovation. As kick the bucket thickness and speed increment, memory and program conduct turn out to be progressively critical in characterizing design exchange offs. While innovation empowers progressively complex processor usage, there are physical, and program conduct cutoff points to the handiness of this multifaceted nature. Physical cutoff points incorporate gadget confines and reasonable breaking points on power and cost. Programs conduct limits result from capricious occasions happening amid execution. Designs and usage that traverse these points of confinement are fundamental to the advancement of the microchip. 

Keyword: parallelism, microprocessor, bit-level, 32-bit


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